As the size and dimensions of transistors are reduced, shallower source and drain regions must be created. However, the high doping concentrations that are required for these shallow source and drain regions lead to an increase in the electric field in the channel of the device. This electric field, if large enough, can cause “hot carrier” problems, whereby electrons in the channel region gain enough energy to be ejected from the channel region and into the gate dielectric. This “hot carrier” phenomenon leads to long-term device degradation and reduced reliability.
One approach to minimize the “hot carrier” problem is by using a double diffused drain (DDD) method, in which two implants are performed to create source and drain regions. For example, a DDD is often used as a source or drain in a high voltage metal oxide semiconductor (HVMOS) transistor. A DDD also, in addition to immunizing against “hot carrier” problems, provides a high breakdown voltage for a HVMOS transistor and prevents electrostatic discharge that may result in the destruction of a semiconductor device.
These DDDs can be formed through a variety of methods. FIGS. 1A through 1D illustrate one such method. Referring first to FIG. 1A, a substrate 101 is provided with isolation regions 103 formed thereon. A transistor gate stack 105 is formed on the substrate 101, the transistor gate stack 105 comprising of a gate dielectric 107 and a gate electrode 109. FIG. 1B shows a first implantation of one species, such as phosphorous, to form a first source/drain region 111. FIG. 1C shows a second implantation of a different species, such as arsenic, to form a second source/drain region 113 overlying the first source/drain region 111. Finally, FIG. 1D shows the completed DDD after a thermal anneal has been performed in order to drive in the first source/drain region 111.
Unfortunately, this process is not ideal for the manufacturing of semiconductor devices. In order to complete this process, a thermal anneal must be performed in order to get the desired implantation. This thermal anneal is very heat intensive, and requires extra thermal budget in order to complete, which leads to higher manufacturing costs.
FIGS. 2A through 2D illustrate another method for forming DDDs. Referring first to FIG. 2A, substrate 201 having isolation regions 203 and a transistor gate 205 formed thereon is shown, wherein the transistor gate 205 comprises a gate dielectric 207 and gate electrode 209. Similar to the process described above with reference to FIG. 1B, FIG. 2B illustrates a first implantation to form a first source/drain region 211. FIG. 2C shows the formation of a mask layer 213 over the substrate 201, the isolation regions 203, and the transistor gate stack 205. FIG. 2D shows the resulting structure after a second implantation has been performed to form a second source/drain region 215, and the mask layer 213 has been removed.
Unfortunately, this is not an ideal process either. By using the masking layer, another step is included in what is already a complicated process for making semiconductor devices, thereby adding time, money, and preparation to the process.
Because of these and other problems associated with the manufacturing of DDDs in semiconductor devices, a new method for fabricating DDDs is needed.